Event Id	Proper Counters		Comments
[1m0xff[0m		CCNT			Core clock tick
[1m0xfe[0m		CCNT			Core clock tick (64 clock base)
[1m0x0[0m		PMN0,PMN1,PMN2,PMN3	L1 I-Cache miss
[1m0x3[0m		PMN0,PMN1,PMN2,PMN3	I-TLB miss
[1m0x4[0m		PMN0,PMN1,PMN2,PMN3	D-TLB miss
[1m0x5[0m		PMN0,PMN1,PMN2,PMN3	B and BL instruction retired
[1m0x6[0m		PMN0,PMN1,PMN2,PMN3	Branch mispredicted
[1m0x7[0m		PMN0,PMN1,PMN2,PMN3	Instruction executed
[1m0x9[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache buffer full stall (sequence)
[1m0xa[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache access
[1m0xb[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache miss
[1m0xc[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache write back
[1m0xd[0m		PMN0,PMN1,PMN2,PMN3	Software change of PC
[1m0xe[0m		PMN0,PMN1,PMN2,PMN3	Branch retired
[1m0x18[0m		PMN0,PMN1,PMN2,PMN3	All changes to the PC
[1m0x19[0m		PMN0,PMN1,PMN2,PMN3	Pipeline flush
[1m0x20[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache request
[1m0x21[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache data request
[1m0x22[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache instruction request
[1m0x23[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache miss
[1m0x24[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache data miss
[1m0x25[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache instruction fetch miss
[1m0x26[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache read miss
[1m0x27[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache data read request
[1m0x28[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache write miss
[1m0x29[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache data write request
[1m0x2a[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache line writeback
[1m0x2b[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache snoop or snoop confirm access
[1m0x2c[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache snoop miss
[1m0x2d[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache active
[1m0x2e[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache push access
[1m0x2f[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache access
[1m0x44[0m		PMN0,PMN1,PMN2,PMN3	Bus initiated data bus transaction
[1m0x49[0m		PMN0,PMN1,PMN2,PMN3	Retired bus transaction
[1m0x50[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache line allocation
[1m0x51[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache line update
[1m0x52[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache recirculated operation
[1m0x53[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache snoop request
[1m0x54[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache snoop confirm
[1m0x55[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache push request
[1m0x56[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache push update
[1m0x57[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache push allocation
[1m0x58[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache special operation
[1m0x59[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache snoop hit on clean cache line
[1m0x5a[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache snoop hit on dirty cache line
[1m0x60[0m		PMN0,PMN1,PMN2,PMN3	Address transaction retry
[1m0x61[0m		PMN0,PMN1,PMN2,PMN3	Snoop transaction retry
