Event Id	Proper Counters		Comments
[1m0xffff[0m		Timer			Timer
[1m0xff[0m		CCNT			Core clock tick
[1m0xfe[0m		CCNT			Core clock tick (64 clock base)
[1m0xc[0m		PMN0,PMN1,PMN2,PMN3	Software change of PC
[1m0xd[0m		PMN0,PMN1,PMN2,PMN3	Branch executed
[1m0xe[0m		PMN0,PMN1,PMN2,PMN3	Procedure return executed
[1m0x10[0m		PMN0,PMN1,PMN2,PMN3	Branch mispredicted or not predicted
[1m0x12[0m		PMN0,PMN1,PMN2,PMN3	Predictable branches
[1m0x63[0m		PMN0,PMN1,PMN2,PMN3	Branch retired
[1m0x72[0m		PMN0,PMN1,PMN2,PMN3	Branch mispredicted
[1m0x81[0m		PMN0,PMN1,PMN2,PMN3	Branches taken
[1m0x1[0m		PMN0,PMN1,PMN2,PMN3	L1 I-Cache miss
[1m0x3[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache miss
[1m0x4[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache access
[1m0x40[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache read hit
[1m0x41[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache read miss
[1m0x42[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache write hit
[1m0x43[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache write miss
[1m0x45[0m		PMN0,PMN1,PMN2,PMN3	L1 I-Cache bus request
[1m0x4f[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache write hit
[1m0x50[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache write miss
[1m0x51[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache read count
[1m0x60[0m		PMN0,PMN1,PMN2,PMN3	L1 I-Cache read miss
[1m0x6a[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache latency
[1m0x70[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache access, including non-cacheable requests
[1m0x79[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache read hit
[1m0x7a[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache read miss
[1m0x7b[0m		PMN0,PMN1,PMN2,PMN3	L2-Cache eviction
[1m0x83[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache read beat
[1m0x84[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache write beat
[1m0x8a[0m		PMN0,PMN1,PMN2,PMN3	L1 I-Cache read beat
[1m0x2[0m		PMN0,PMN1,PMN2,PMN3	I-TLB miss
[1m0x5[0m		PMN0,PMN1,PMN2,PMN3	D-TLB miss
[1m0x6[0m		PMN0,PMN1,PMN2,PMN3	Data read executed
[1m0x7[0m		PMN0,PMN1,PMN2,PMN3	Data write executed
[1m0x44[0m		PMN0,PMN1,PMN2,PMN3	MMU bus request
[1m0x4c[0m		PMN0,PMN1,PMN2,PMN3	Data write access
[1m0x4d[0m		PMN0,PMN1,PMN2,PMN3	Data read access
[1m0x61[0m		PMN0,PMN1,PMN2,PMN3	I-TLB main MMU miss
[1m0x65[0m		PMN0,PMN1,PMN2,PMN3	MMU read beat
[1m0x71[0m		PMN0,PMN1,PMN2,PMN3	D-TLB main MMU miss
[1m0x78[0m		PMN0,PMN1,PMN2,PMN3	BIU simultaneous access
[1m0x80[0m		PMN0,PMN1,PMN2,PMN3	TLB miss
[1m0x87[0m		PMN0,PMN1,PMN2,PMN3	BIU any access
[1m0x88[0m		PMN0,PMN1,PMN2,PMN3	Main TLB miss caused by I-Cache
[1m0x89[0m		PMN0,PMN1,PMN2,PMN3	Main TLB miss caused by D-Cache
[1m0x8[0m		PMN0,PMN1,PMN2,PMN3	Instruction executed
[1m0x9[0m		PMN0,PMN1,PMN2,PMN3	Exception taken
[1m0xa[0m		PMN0,PMN1,PMN2,PMN3	Exception return
[1m0xb[0m		PMN0,PMN1,PMN2,PMN3	Writes context ID register
[1m0xf[0m		PMN0,PMN1,PMN2,PMN3	Unaligned access
[1m0x11[0m		PMN0,PMN1,PMN2,PMN3	Cycle count
[1m0x46[0m		PMN0,PMN1,PMN2,PMN3	Write buffer write latency
[1m0x47[0m		PMN0,PMN1,PMN2,PMN3	Hold LDM/STM
[1m0x48[0m		PMN0,PMN1,PMN2,PMN3	No dual cflag
[1m0x49[0m		PMN0,PMN1,PMN2,PMN3	No dual register plus
[1m0x4a[0m		PMN0,PMN1,PMN2,PMN3	Load/store ROB0 on hold
[1m0x4b[0m		PMN0,PMN1,PMN2,PMN3	Load/store ROB1 on hold
[1m0x4e[0m		PMN0,PMN1,PMN2,PMN3	A2 stage stall
[1m0x62[0m		PMN0,PMN1,PMN2,PMN3	Single issue
[1m0x64[0m		PMN0,PMN1,PMN2,PMN3	ROB full
[1m0x66[0m		PMN0,PMN1,PMN2,PMN3	Write buffer write beat
[1m0x67[0m		PMN0,PMN1,PMN2,PMN3	Dual issue
[1m0x68[0m		PMN0,PMN1,PMN2,PMN3	No dual raw
[1m0x69[0m		PMN0,PMN1,PMN2,PMN3	Hold issue stage
[1m0x74[0m		PMN0,PMN1,PMN2,PMN3	A1 stage stall
[1m0x77[0m		PMN0,PMN1,PMN2,PMN3	No dual register file
[1m0x82[0m		PMN0,PMN1,PMN2,PMN3	Write buffer full
[1m0x85[0m		PMN0,PMN1,PMN2,PMN3	No dual hardward
[1m0x86[0m		PMN0,PMN1,PMN2,PMN3	No dual multiple
[1m0xc0[0m		PMN0,PMN1,PMN2,PMN3	WMMX2 store FIFO full
[1m0xc1[0m		PMN0,PMN1,PMN2,PMN3	WMMX2 finish FIFO full
[1m0xc2[0m		PMN0,PMN1,PMN2,PMN3	WMMX2 instruction FIFO full
[1m0xc3[0m		PMN0,PMN1,PMN2,PMN3	WMMX2 instruction retired
[1m0xc4[0m		PMN0,PMN1,PMN2,PMN3	WMMX2 busy
[1m0xc5[0m		PMN0,PMN1,PMN2,PMN3	WMMX2 hold issue stage
[1m0xc6[0m		PMN0,PMN1,PMN2,PMN3	WMMX2 hold write back stage
[1m0x75[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache read latency
[1m0x76[0m		PMN0,PMN1,PMN2,PMN3	L1 D-Cache write latency
[1m0x8b[0m		PMN0,PMN1,PMN2,PMN3	Predicted branch count
[1m0xf0[0m		PMN0,PMN1,PMN2,PMN3	L0 I-Cache line fill
[1m0xf1[0m		PMN0,PMN1,PMN2,PMN3	L0 I-Cache hit prefetch buffer
[1m0x1D[0m		MC0,MC1,MC2,MC3		Auto-refresh (non-idle)
[1m0x1C[0m		MC0,MC1,MC2,MC3		Auto-refresh (all)
[1m0x1A[0m		MC0,MC1,MC2,MC3		Write request
[1m0x19[0m		MC0,MC1,MC2,MC3		Read request
[1m0x18[0m		MC0,MC1,MC2,MC3		All data request
[1m0x16[0m		MC0,MC1,MC2,MC3		Write command
[1m0x15[0m		MC0,MC1,MC2,MC3		Read command
[1m0x14[0m		MC0,MC1,MC2,MC3		Read + Write command
[1m0x10[0m		MC0,MC1,MC2,MC3		ACTIVE command
[1m0xe[0m		MC0,MC1,MC2,MC3		PRECHARGE command (non-data)
[1m0xd[0m		MC0,MC1,MC2,MC3		PRECHARGE command (data)
[1m0xc[0m		MC0,MC1,MC2,MC3		PRECHARGE command (all)
[1m0x4[0m		MC0,MC1,MC2,MC3		Non-idle cycles with no data bus utilization
[1m0x3[0m		MC0,MC1,MC2,MC3		(reserved) Non-idle cycles waiting for tWTR
[1m0x2[0m		MC0,MC1,MC2,MC3		Non-idle cycles when waiting for tRFC
[1m0x1[0m		MC0,MC1,MC2,MC3		Idle cycles (Memory Controller pipeline empty)
[1m0x0[0m		MC0,MC1,MC2,MC3		Clock
